1. Field of the Invention
The present invention relates to a voltage conversion circuit and a semiconductor device using the same. More particularly, the present invention relates to a voltage conversion circuit for converting signal voltage levels between circuits having different power source voltages and a semiconductor device using the same.
2. Description of the Related Art
Conventionally, when a signal is transferred between circuits having different power source voltages, a voltage conversion circuit (level shifter circuit) which converts the amplitude levels of signal voltages between these circuits is used as an interface circuit.
For example, the circuit configuration and operation of a voltage conversion circuit will be described below, which has a plurality of circuit sections comprising MOS transistors and driven by different power source voltages and which functions as an interface circuit.
FIG. 7 is a circuit diagram showing a voltage conversion circuit 100 which functions as the above-described interface circuit. The voltage conversion circuit 100 comprises an inverter circuit 70 and a voltage output circuit 80.
The power source voltage and reference voltage (LOW level) of the voltage output circuit 80 are VDD1 and VSS1, respectively. The power source voltage and reference voltage (LOW level) of the inverter circuit 70 are VDD2 and VSS1, respectively. Here, voltage conditions are VDD1 greater than VDD2 and VSS1=VSS2=GND level. These conditions are referred to as voltage conditions A.
In the voltage output circuit 80, P-type MOS transistors 80c and 80d are connected in parallel. The source terminals of the P-type MOS transistor 80c and 80d are each connected to the power source voltage VDD1. The drain terminals of the P-type MOS transistors 80c and 80d are connected to the drain terminals of N-type MOS transistors 80a and 80b, respectively. The gate terminals of the P-type MOS transistors 80a and 80d are connected to the drain terminals of the N-type MOS transistors 80b and 80a, respectively. The drain terminals of the P-type MOS transistor 80d and the N-type MOS transistor 80b are the output terminal (output node B) of the voltage conversion circuit 100. The source terminals of the N-type MOS transistors 80a and 80b are each connected to VSS1=GND (earth). The gate terminal of the N-type MOS transistor 80a is connected to the input terminal of the inverter circuit 70. The gate terminal of the N-type MOS transistor 80b is connected to the output terminal of the inverter circuit 70.
The inverter circuit 70 comprises a P-type MOS transistor 70b and the N-type MOS transistor 70a. The drain and gate terminals of the P-type MOS transistor 70b are connected to the drain and gate terminals of the N-type MOS transistor 70a, respectively. The drain terminals of the P-type MOS transistor 70b and the N-type MOS transistor 70a are each the output terminal of the inverter circuit 70, while the gate terminals of the P-type MOS transistor 70b and the N-type MOS transistor 70a are each the input terminal of the inverter circuit 70. The input terminal of the inverter circuit 70 is the input terminal (input node A) of the voltage conversion circuit 100. The source terminals of the P-type MOS transistor 70b and the N-type MOS transistor 70a are connected to the power source voltage VDD2 and VSS2=GND (earth), respectively.
In the voltage conversion circuit 100 of FIG. 7, when a signal voltage A (HIGH level: VDD2, LOW level: VSS2) is input to the input node A, a signal voltage B (HIGH level: VDD1, LOW level: VSS1) is output through the output node B so that the HIGH level (VDD2) of the signal voltage A is converted to the HIGH level (VDD1) of the signal voltage B (voltage conversion). This operation will be described below in more detail. Note that the HIGH level and the LOW level are referred to as the H state and the L state, respectively.
It is now assumed that the input node A is in the H (VDD2) state. In this case, the input terminal of the inverter circuit 70 and the gate terminal of the N-type MOS transistor 80a of the voltage output circuit 80 are in the H state, and the N-type MOS transistor 80a is in the ON state. In this case, the output terminal of the inverter circuit 70 is in the L state, while the drain terminal of the N-type MOS transistor 80a is in the L state. When the output terminal of the inverter circuit 70 is in the L state, the gate terminal of the N-type MOS transistor 80b is in the L state, so that the N-type MOS transistor 80b is in the OFF state and the drain terminal of the N-type MOS transistor 80b is in the H state.
When the drain terminal of the N-type MOS transistor 80b is in the H state, the gate terminal of the P-type MOS transistor 80c is also in the H state and the P-type MOS transistor 80c is in the OFF state. In this case, the power source voltage VDD1 of the voltage output circuit 80 is not applied to the drain terminal of the N-type MOS transistor 80a, so that the drain terminal of the N-type MOS transistor 80a is maintained in the L state.
When the drain terminal of the N-type MOS transistor 80a is in the L state, the gate terminal of the P-type MOS transistor 80d is also in the L state, so that the P-type MOS transistor 80d is in the ON state. In this case, the power source voltage VDD1 of the voltage output circuit 80 is applied to the drain terminal of the N-type MOS transistor 80b. In this case, the N-type MOS transistor 80b is in the OFF state, while the H state (VDD1) of the drain terminal of the N-type MOS transistor 80b is output through the output terminal (output node B).
The same applies to the case where the input node A is in the L (VSS2) state. In this case, the output node B is in the L (VSS1) state, where VSS1=VSS2=GND.
Next, only an inverter circuit is provided between the circuits having different power source voltages instead of the voltage conversion circuit 100. The operation of this circuit 110 configuration will be described below with reference to FIG. 8.
The inverter circuit 110 of FIG. 8 comprises a P-type MOS transistor 90b and an N-type MOS transistor 90a. The drain and gate terminals of the P-type MOS transistor 90b are connected to the drain and gate terminals of the N-type MOS transistor 90a, respectively. The drain terminals of the P-type MOS transistor 90b and the N-type MOS transistor 90a are the output terminal (output node B) of the inverter circuit 110. The gate terminals of the P-type MOS transistor 90b and the N-type MOS transistor 90a are the input terminal (input node A) of the inverter circuit 110. The source terminals of the P-type MOS transistor 90b and the N-type MOS transistor 90a are connected to the power source voltage VDD1 and VSS1=GND (earth), respectively.
It is now assumed that a signal voltage A (H: VDD2, L: VSS2) satisfying the above-described voltage conditions A (VDD1 greater than VDD2 and VSS1=VSS2=GND level) is applied to the input node A of the inverter circuit 110. The operation of the inverter circuit in this case will be described.
When a potential difference between VDD1 and VDD2 (=VDD1-VDD2) is less than a threshold voltage of the P-type MOS transistor 90b of FIG. 8, if an H state (VDD2) signal voltage A is input to the input node A, the P-type MOS transistor 90b is in the OFF state. In this case, the N-type MOS transistor 90a is in the ON state and the output node B is in the L state (VSS1). Alternatively, when an L state (VSS2) signal voltage A is input to the input node A, the P-type MOS transistor 90b is in the ON state and the N-type MOS transistor 90a is in the OFF state, so that the output node B is in the H state (VDD1). In this case, the inverter circuit is normally operated to perform voltage conversion (VDD2xe2x86x92VDD1) between the input node A and the output node B.
However, when the potential difference between VDD1 and VDD2 is greater than or equal to the threshold voltage of the P-type MOS transistor 90b in the inverter circuit 10 of FIG. 8, if the H state (VDD2) signal voltage A is input to the input node A, both the P-type MOS transistor 90b and the N-type MOS transistor 90a in the inverter circuit 110 of FIG. 8 are in the ON state. In this case, a current flows between the power source voltage VDD1 and VSS1 (earth). Therefore, in the CMOS transistor inverter circuit 110 comprising the P-type MOS transistor 90b and the N-type MOS transistor 90a, when the signal voltage A is in the H state, a current consistently flows between the power source voltage VDD1 and VSS1 (earth) and thus low power consumption drive cannot be achieved.
Therefore, in the circuits in FIGS. 7 and 8, the voltage output circuit 80 of FIG. 7 is required to achieve the operation that when the signal voltage A (H: VDD2, L: VSS2) satisfying the voltage conditions A is input to the input node A, the signal voltage B (H: VDD1, L: VSS1) is normally output through the output node B.
In recent years, there is a tendency to often use a circuit capable of operating under signal input conditions, such as the above-described voltage conditions A, for use in a system apparatus comprising a combination of IC chips having different power source voltages, and a system apparatus comprising voltage conversion circuits having different operational voltages, different functions, or the like, on one chip.
The voltage conversion circuit 100 of FIG. 7 is a circuit which has only a function of performing voltage conversion between the input voltage and the output voltage. In addition, the interface circuit may have a stand-by function, may be provided between voltage conversion circuit blocks having different functions on one chip, or the like. FIG. 9 is a circuit diagram showing an exemplary interface circuit (voltage conversion circuit 120) having a stand-by function.
The voltage conversion circuit 120 of FIG. 9 has a buffer circuit 50, a NOR circuit 60, an inverter circuit 70, and a voltage output circuit 80.
The AD terminal of the NOR circuit 60 is the input terminal of the voltage conversion circuit 120. The CEB terminal of the buffer circuit 50 is the control terminal of the voltage conversion circuit 120. The ADOUTB terminal of the voltage output circuit 80 is the output terminal of the voltage conversion circuit 120.
The voltage conversion circuit 120 controls an AD (address) signal (H state: VDD2, L state: VSS2), which is input to the AD terminal of the NOR circuit 60 (i.e., the input terminal of the voltage conversion circuit 120) and satisfies the above-described voltage conditions A, based on a CEB signal which is input to the CEB terminal of the buffer circuit 50. The voltage conversion circuit 120 outputs an ADOUTB signal (H state: VDD1, L state: VSS1), which is obtained by subjecting the AD signal to voltage conversion, through the ADOUTB terminal of the voltage output circuit 80 (i.e., the output terminal of the voltage conversion circuit 120. The CEB signal is a control signal which is used to switch the state of the voltage conversion circuit 120 between the stand-by state and the operation state. Note that the inverter circuit 70 and the voltage output circuit 80 have a circuit configuration similar to that of FIG. 7.
In the buffer circuit 50, two inverter circuits comprising CMOS transistors are connected in series. The inverter circuit at the first stage comprises a P-type MOS transistor 50b and an N-type MOS transistor 50a. The drain and gate terminals of the P-type MOS transistor 50b are connected to the drain and gate terminals of the N-type MOS transistor 50a. The drain terminals of the P-type MOS transistor 50b and the N-type MOS transistor 50a are each the output terminal of the first stage inverter circuit and are connected to the input terminal of the inverter circuit at the second stage. The gate terminals of the P-type MOS transistor 50b and the N-type MOS transistor 50a are each the input terminal of the buffer circuit 50, and function as a CEB terminal through which a switching signal (CEB signal) for switching between the stand-by state and the operation state is input. The source terminals of the P-type MOS transistor 50b and the N-type MOS transistor 50a are connected to the power source voltage VDD2 and VSS2=GND (earth), respectively.
The second stage inverter circuit also comprises a P-type MOS transistor 50d and an N-type MOS transistor 50c, and has connections similar to those in the first stage inverter circuit. The gate terminals of the P-type MOS transistor 50d and the N-type MOS transistor 50c are each the input terminal of the second stage inverter circuit and are connected to the output terminal of the first stage inverter circuit. The drain terminals of the P-type MOS transistor 50d and the N-type MOS transistor 50c are each the output terminal of the buffer circuit 50 and are each connected to a node A. The source terminals of the P-type MOS transistor 50d and the N-type MOS transistor 50c are connected to the power source voltage VDD2 and VSS2=GND (earth), respectively.
The NOR circuit 60 has P-type MOS transistors 60c and 60d connected to each other in series and N-type MOS transistors 60a and 60b connected to each other in parallel. The source and drain terminals of the P-type MOS transistor 60d are connected to the power source voltage VDD2 and the source terminal of the P-type MOS transistor 60c, respectively. The drain terminal of the P-type MOS transistor 60c is connected to the drain terminals of the N-type MOS transistor 60a and 60b. The drain terminal of the P-type MOS transistor 60c and the drain terminals of the N-type MOS transistors 60a and 60b are the output terminal of the NOR circuit 60 and are connected to a node B. The source terminals of the N-type MOS transistors 60a and 60b are each connected to VSS2=GND (earth). The gate terminal of the N-type MOS transistor 60a is connected to the output terminal of the buffer circuit 50 via the node A and to the gate terminal of the P-type MOS transistor 60c. The gate terminal of the N-type MOS transistor 60b is connected to the gate terminal of the P-type MOS transistor 60d and is the input terminal of the NOR circuit 60, which is an AD terminal through which an AD signal (address signal) is input as an input signal.
The output terminal of the NOR circuit 60 is connected via the node B to the input terminal of the inverter circuit 70 and the gate terminal of the N-type MOS transistor 80a in the voltage output circuit 80.
The inverter circuit 70 and the voltage output circuit 80 have a circuit configuration similar to the circuit shown in FIG. 7. The output terminal of the inverter circuit 70 is connected via a node C to the gate terminal of the N-type MOS transistor 80b in the voltage output circuit 80.
Next, the operation of the voltage conversion circuit 120 of FIG. 9 will be described below. The voltage conversion circuit 120 is in the operation state when the CEB signal input through the CEB terminal (control terminal) is in the L state; and is in the stand-by state when the CEB signal is in the H state.
When the CEB signal is in the H state (VDD2), the H state CEB signal is input to the input terminal of the buffer circuit 50 and an H state output signal is output through the output terminal of the buffer circuit 50. The H state output signal is input via the node A to the gate terminals of the P-type MOS transistor 60c and the N-type MOS transistor 60a in the NOR circuit 60. In this case, the P-type MOS transistor 60c goes to the OFF state, the N-type MOS transistor 60a goes to the ON state, and the drain terminal of the N-type MOS transistor 60a goes to the L state.
In this case, when the AD signal input to the AD terminal of the NOR circuit 60 is either in the H state or the L state, the output terminal of the NOR circuit 60 connected to the drain terminal of the N-type MOS transistor 60a is in the L state. Therefore, the L state output signal is output via the node B to the inverter circuit 70 and the voltage output circuit 80. When the inverter circuit 70 and the voltage circuit 80 receive the L state signal, the output terminal (ADOUTB terminal) of the voltage output circuit 80 is in the L state as described for the operation of the voltage conversion circuit 100 of FIG. 7.
Therefore, in the voltage conversion circuit 120, if the CEB signal input to the CEB terminal (control terminal) is in the H state, the ADOUTB signal output through the ADOUTB terminal (output terminal) is consistently in the L state no matter whether the AD signal input to the AD terminal (input terminal) is in the H state or the L state, thereby maintaining the stand-by state of the voltage conversion circuit 120.
Next, when the CEB signal is in the L state (VSS2), the L state CEB signal is input to the input terminal of the buffer circuit 50 and an L state output signal is output through the output terminal of the buffer circuit 50. This L state output signal is input via the node A to the gate terminals of the P-type MOS transistor 60c and N-type MOS transistor 60a in the NOR circuit 60. In this case, the P-type MOS transistor 60c goes to the ON state and the N-type MOS transistor 60a goes to the OFF state.
In this case, if the AD signal input the AD terminal of the NOR circuit 60 is in the H state, the AD signal is input to the gate terminals of the P-type MOS transistor 60d and the N-type MOS transistor 60b. In this case, the P-type MOS transistor 60d goes to the OFF state and the drain terminal of the N-type MOS transistor 60b goes to the L state. When the drain terminal of the N-type MOS transistor 60b is in the L state, the output terminal of the NOR circuit 60 connected to the drain terminal of the N-type MOS transistor 60b is in the L state. In this case, an L state output signal is output via the node B to the inverter circuit 70 and the voltage output circuit 80. When the inverter circuit 70 and the voltage output circuit 80 receive the L state signal, the ADOUTB terminal (output terminal) of the voltage output circuit 80 goes to the L state.
When the AD signal input to the AD terminal of the NOR circuit 60 is in the L state, the P-type MOS transistor 60d is in the ON state and the N-type MOS transistor 60b is in the OFF state. In this case, the drain terminals of the N-type MOS transistor 60a and the N-type MOS transistor 60b are in the H state, and the P-type MOS transistor 60c and the P-type MOS transistor 60d are in the ON state. Therefore, the output terminal of the NOR circuit 60 connected to the drain terminals of the P-type MOS transistor 60c and the N-type MOS transistor 60b is supplied with the power source voltage VDD2 to be in the H state (VDD2), and an H state output signal is output via the node B to the inverter circuit 70 and the voltage output circuit 80. When the H state signal is input to the inverter circuit 70 and the voltage output circuit 80, the ADOUTB terminal (output terminal) of the voltage output circuit 80 goes to the H state as described for the operation of voltage conversion circuit 100 of FIG. 7.
Therefore, if the CEB signal input to the CEB terminal (control terminal) of the voltage conversion circuit 120 is in the L state, the ADOUTB signal output through the ADOUTB terminal (output terminal) is in the L state or the H state based on whether the AD signal input through the AD terminal (input terminal) is in the H state or in the L state, and the operation state of the voltage conversion circuit 120 is maintained.
FIG. 10 is a timing chart showing the CEB signal, the AD signal, the ADOUTB signal, and signals on the nodes A, B, C and D when the voltage conversion circuit 120 of FIG. 9 is released from the stand-by state (i.e., the circuit 120 goes to the operation state). Here, CEB, AD, ADOUTB, and Nodes A, B, C and D respectively indicate the signal waveforms of the CEB signal, the AD signal, the ADOUTB signal, and the signals on the node A, B, C and D (also referred to as node A signal, node B signal, node C signal and node D signal, respectively).
When the voltage conversion circuit 120 of FIG. 9 is released from the stand-by state, the CEB signal input to the buffer circuit 50 goes from the H state (VDD2) to the L state (VSS2=GND). In this case, the output signal of the buffer circuit 50 on the node A connected to the output terminal of the buffer circuit 50 goes from the H state to the L state where the transition is delayed by a delay time (2T) due to the buffer circuit 50, resulting in a signal waveform indicated by Node A in FIG. 10 (H state: VDD2, L state: GND).
In this case, it is assumed that the AD signal input to the NOR circuit 60 is fixed to the L state (VSS2=GND) as indicated by AD in FIG. 10. In this case, the output signal of the NOR circuit 60 on the node B connected to the output terminal of the NOR circuit 60 of FIG. 9 goes from the L state to the H state where the transition is delayed at a delay time (1T) due to the NOR circuit 60, resulting in a signal waveform indicated by Node B in FIG. 10 (H state: VDD2, L state: GND).
The output signal of the inverter circuit 70 on the node C connected to the output terminal of the inverter circuit 70 goes from the H state to the L state where the transition is delayed by a delay time (1T) due to the inverter circuit 70, resulting in a signal waveform indicated by Node C in FIG. 10 (H state: VDD2, L state: GND).
A signal on the node D connected to the drain terminal of the N-type MOS transistor 80a is changed based on the signal state on the node B input to the gate terminal of the N-type MOS transistor 80a, resulting in a signal waveform which changes from the H state to the L state as indicated by Node D in FIG. 10 (H state: VDD1, L state: GND).
The ADOUTB signal output through the ADOUTB terminal (output terminal) of the voltage conversion circuit 120 goes from the L state to the H state in accordance with the timing of the signal waveforms indicated by Node B and Node C in FIG. 10, resulting in a signal waveform indicated by ADOUTB in FIG. 10 (H state: VDD1, L state: GND).
As shown in FIG. 10, the signal on the node C is delayed by 1T relative to the signal on the node B. Therefore, in the operation of the voltage output circuit 80 (FIG. 9), the signal on the node B (FIG. 9) goes from the L state to the H state based on the output signal of the NOR circuit 60 and thus the N-type MOS transistor 80a goes from the OFF state to the ON state. When the N-type MOS transistor 80a goes to the ON state, the drain terminal of the N-type MOS transistor 80a goes to the L state, so that the signal on the node D of the voltage output circuit 80 goes from the H state (VDD1) to the L state (GND). Thereafter, when the signal on the node C (FIG. 9) goes from the H state to the L state based on the output signal of the inverter circuit 70, the N-type MOS transistor 80b goes from the ON state to the OFF state. When the N-type MOS transistor 80b goes from the ON state to the OFF state, the P-type MOS transistor 80d goes from the OFF state to the ON state in association with the transition of the signal on the above-described node D from the H state to the L state. In this case, the power source voltage VDD1 is applied to the drain terminal of the N-type MOS transistor 80b, the ADOUTB signal output from the ADOUTB terminal connected to the drain terminal goes from the L state (GND) to the H state (VDD1). In this case, the timing of the transition of the P-type MOS transistor 80d from the OFF state to the ON state is substantially the same as the timing of the transition of the N-type MOS transistor 80b from the ON state to the OFF state.
The transition of the ADOUTB signal in the voltage output circuit 80 from the L state to the H state starts from the transition starting point of the signal waveform on the node B in FIG. 10 from the L state to the H state. Therefore, the elapsed time from the starting point is a delay time (AT).
Therefore, when the voltage conversion circuit 120 is released from the stand-by state, the delay time between the release and the outputting of the ADOUTB signal through the ADOUTB terminal (output terminal) is 2T+AT as indicated by the signal waveform (ADOUTB) in FIG. 10. This delay time starts at the time when the CEB signal reaches a voltage value of (VDD2)/2 from the H state and ends at the time when the ADOUTB signal reaches a voltage value of (VDD1)/2 from the L state.
When the AD signal input to the NOR circuit 60 is fixed to the H state (VDD2), the ADOUTB signal is consistently in the L state. In this case, there is no delay time between the release of the voltage conversion circuit 120 from the stand-by state and the outputting of the ADOUTB signal through the ADOUTB terminal (output terminal).
Therefore, the delay time between the release of the voltage conversion circuit 120 from the stand-by state and the outputting of the ADOUTB signal through the ADOUTB terminal (output terminal) is 2T+AT at most (worst case).
Next, it is now assumed in the voltage conversion circuit 120 of FIG. 9, after releasing the voltage conversion circuit 120 from the stand-by state, the CEB signal input to the buffer circuit 50 is maintained in the L state and the AD signal input to the NOR circuit 60 goes from the L state to the H state.
FIG. 11 is a timing chart showing the CEB signal, the AD signal, the ADOUTB signal and signals on the nodes A, B, C and D when the AD signal goes from the L state to the H state after the voltage conversion circuit 120 is released from the stand-by state. Here, CEB, AD, ADOUTB and Nodes A, B, C and D indicate the signal waveforms of the CEB signal, the AD signal, the ADOUTB signal and signals on the nodes A, B, C and D, respectively.
The CEB signal is fixed to the L state (GND) since the voltage conversion circuit 120 has been released from the stand-by state, as indicated by CEB in FIG. 11.
The signal on the node A is in the L state because of the L state (GND) CEB signal and therefore has no delay time, resulting in a signal waveform indicated by Node A in FIG. 11 (L state: GND).
The AD signal has a signal waveform which transitions from the L state to the H state (H state: VDD2, L state: GND) as indicated by AD in FIG. 11.
The signal on the node B goes from the H state to the L state where the transition is delayed by a delay time (1T) due to the NOR circuit 60 which receives the AD signal, resulting in a signal waveform indicated by Node B in FIG. 11 (H state: VDD2, L state: GND).
The signal on the node C goes from the L state to the H state where the transition is delayed by a delay time (1T) due to the inverter circuit 70, resulting in a signal waveform indicated by Node C in FIG. 11 (H state: VDD2, L state: GND).
The signal on the node D is transitioned based on the switching of the N-type MOS transistor 80a, resulting in a signal waveform which transitions from the L state to the H state as indicated by Node D in FIG. 11 (H state: VDD1, L state: GND).
The ADOUTB signal is transitioned in accordance with the timings of the signal waveforms indicated by Node B and Node C in FIG. 11, resulting in a signal waveform which transitions from the H state to the L state as indicated by ADOUTB in FIG. 11 (H state: VDD1, L state: GND).
As indicated in FIG. 11, the signal on the node C is delayed by 1T relative to the signal on the node B. Therefore, in the operation of the voltage output circuit 80 of FIG. 9, the signal on the node B (FIG. 9) is first transitioned from the H state to the L state based on the output signal of the NOR circuit 60, whereby the N-type MOS transistor 80a goes from the ON state to the OFF state. In this case, the ADOUTB signal output through the ADOUTB terminal of the voltage output circuit 80 is in the H state, and therefore, the N-type MOS transistor 80a and the P-type MOS transistor 80c are in the OFF state. As a result, the signal on the node D in the voltage output circuit 80 is in the floating state. Note that since nowhere supplies a current to the node D, the signal on the node D is maintained in the L state.
Thereafter, when the signal on the node C (FIG. 9) goes from the L state to the H state based on the output signal of the inverter circuit 70, the N-type MOS transistor 80b goes from the OFF state to the ON state. Here, for the first time, the ADOUTB signal goes from the H state to the L state. When the ADOUTB signal goes from the H state to the L state, the P-type MOS transistor 80c goes from the OFF state to the ON state and the signal on the node D, which has been in the floating state, goes from the L state to the H state. When the signal on the node D goes from the L state to the H state, the P-type MOS transistor 80d goes from the ON state to the OFF state, resulting in acceleration of the transition of the ADOUTB signal from the H state to the L state.
The transition of the ADOUTB signal in the voltage output circuit 80 from the H state to the L state starts from the transition starting point of the signal waveform indicated by Node C in FIG. 11 from the L state to the H state. Therefore, the elapsed time from this starting point is a delay time (BT).
Therefore, when only the AD signal input through the AD terminal (input terminal) goes from the L state to the H state after the voltage conversion circuit 120 has been released from the stand-by state, the delay time between the release and the outputting of the ADOUTB signal through the ADOUTB terminal (output terminal) is 1T+BT as indicated by the signal waveform (ADOUTB) in FIG. 11. This delay time starts at the time when the transition of the signal on the node B from the H state to the L state is started and ends at the time when the ADOUTB signal reaches a voltage value of (VDD1)/2 from the H state.
Next, it is assumed that in the voltage conversion circuit 120 (FIG. 9), after releasing the voltage conversion circuit 120 from the stand-by state, the CEB signal input to the buffer circuit 50 is maintained in the L state and the AD signal input to the NOR circuit 60 goes from the H state to the L state.
FIG. 12 is a timing chart showing the CEB signal, the AD signal, the ADOUTB signal and signals on the nodes A, B, C and D when the AD signal goes from the H state to the L state after the voltage conversion circuit 120 has been released from the stand-by state. Here, CEB, AD, ADOUTB, and Nodes A, B, C and D indicate the signal waveforms of the CEB signal, the AD signal, the ADOUTB signal, and signals on the nodes A, B, C and D, respectively.
Since the CEB signal is fixed to the L state (GND) because of the release of the voltage conversion circuit 120 from the stand-by state, as indicated by CEB in FIG. 12.
Since the CEB is maintained in the signal in the L state (GND), the signal on the node A is in the L state and therefore there is no delay time, resulting in a signal waveform indicated by Node A in FIG. 12 (L state: GND).
The AD signal has a signal waveform which transitions from the H state to the L state as indicated by AD in FIG. 12 (H state: VDD2, L state: GND).
The signal on the node B has a signal waveform in which the signal goes from the L state to the H state as indicated by Node B in FIG. 12 where the transition is delayed by a delay time (1T) due to the NOR circuit 60 which receives the AD signal (H state: VDD2, L state: GND).
The signal on the node C has a signal waveform in which the signal goes from the H state to the L state as indicated by Node C in FIG. 12 where the transition is delayed by a delay time (1T) due to the inverter circuit 70 (H state: VDD2, L state: GND).
The signal on the node D is changed based on the switching of the N-type MOS transistor 80a, resulting in a signal waveform which transitions from the H state to the L state as indicated by Node D in FIG. 12 (H state: VDD1, L state: GND).
The ADOUTB signal is changed in accordance with the timings of the signal waveforms indicated by Node B and Node C in FIG. 12, resulting in a signal waveform which transitions from the L state to the H state as indicated by ADOUTB in FIG. 12 (H state: VDD1, L state: GND).
As shown in FIG. 12, the signal on the node C is delayed by 1T relative to the signal on the node B. Therefore, in the operation of the voltage output circuit 80 (FIG. 9), when the signal on the node B is first transitioned from the L state to the H state based on the output signal of the NOR circuit 60, the N-type MOS transistor 80a goes from the OFF state to the ON state. When the N-type MOS transistor 80a goes to the ON state, the drain terminal of the N-type MOS transistor 80a goes to the L state, so that the signal on the node D in the voltage output circuit 80 goes from the H state (VDD1) to the L state (GND). Thereafter, when the signal on the node C (FIG. 9) goes from the H state to the L state based on the output signal of the inverter circuit 70, the N-type MOS transistor 80b goes from the ON state to the OFF state. When the N-type MOS transistor 80b goes from the ON state to the OFF state, the P-type MOS transistor 80d goes from the OFF state to the ON state in association with the transition of the signal on the node D from the H state to the L state. In this case, the power source voltage VDD1 is applied to the drain terminal of the N-type MOS transistor 80b and the ADOUTB signal output through the ADOUTB terminal connected to the drain terminal goes from the L state (GND) to the H state (VDD1). The timing of the transition of the P-type MOS transistor 80d from the OFF state to the ON state is substantially the same as the timing of the transition of the N-type MOS transistor 80b from the ON state to the OFF state, as in the case when the voltage conversion circuit 120 is released from the stand-by state (FIG. 10).
As shown in FIG. 12, the relationship between the signal waveform of the node B and the signal waveform of the node C is such that when the signal waveform of the node B goes from the L state to the H state, the signal waveform of the the node C goes from the H state to the L state based on the transition of the signal waveform of the node B. Thus, the input state of the signal to the voltage output circuit 80 (FIG. 9) is similar to when the voltage conversion circuit 120 is released from the stand-by state (FIG. 10), and therefore, the delay time of the transition of the ADOUTB signal from the L state to the H state is AT.
Therefore, when only the AD signal input through the AD terminal (input terminal) goes from the H state to the L state after the voltage conversion circuit 120 has been released from the stand-by state, the delay time between the release and the outputting of the ADOUTB signal through the ADOUTB terminal (output terminal) is 1T+AT as indicated by the signal waveform (ADOUTB) of FIG. 12. This delay time starts at the time when the transition starting point of the signal on the node B from the L state to the H state is started and ends at when the ADOUTB signal reaches a voltage of (VDD1)/2 from the L state.
The ADOUTB signal and the node D signal indicated by ADOUTB and Node D, respectively, in FIGS. 10, 11 and 12 have opposite voltage polarities. If the signal on the node D in the voltage output circuit 80 is assumed to be the output signal of the voltage conversion circuit 120, the delay time of the node D signal is greater than the delay time of the ADOUTB signal as indicated in FIGS. 11 and 12. This is because the delay time (1T+BT) of the ADOUTB signal going from the H state to the L state (FIG. 11) is substantially the same as the delay time (1T+AT) of the ADOUTB signal going from the L state to the H state (FIG. 12), and therefore, the delay time of the Node D signal going from the L state to the H state is longest. Considering both FIGS. 11 and 12, the delay time of the Node D signal is longer than the delay time of the ADOUTB signal. Therefore, it is not preferable to use the node D signal as the output signal of the voltage conversion circuit 120. Therefore, the ADOUTB signal output through the ADOUTB terminal is used as the output signal of the voltage conversion circuit 120, since when all of the delay time occurred in the release of the voltage conversion circuit 120 from the stand-by state, the delay time occurred in the transition of the AD signal from the L state to the H state after the release of the voltage conversion circuit 120 from the stand-by state, and the delay time occurred in the transition of the AD signal from the H state to the L state, are considered, the delay time of the ADOUTB signal is shorter than the delay time of the Node D signal.
In the voltage conversion circuit 120 (FIG. 9), when the voltage conversion circuit 120 is released from the stand-by state as well as when only the AD signal (address signal) is transitioned to the H or L state after the release of the voltage conversion circuit 120 from the stand-by state, a delay time occurs in the output signal of the voltage conversion circuit 120 as described above. A reduction in this delay time is much required. For example, in general semiconductor memory devices in which an address signal is input and data is output as an output signal, by reducing an access time in the semiconductor memory device, data can be read out at high speed.
However, in the voltage conversion circuit 120 shown in FIG. 9, a large delay time occurs in the output signal of the voltage conversion circuit 120 in an access that the voltage conversion circuit 120 is released from the stand-by state as well as in an access that only an address signal is transitioned to the H or L state after the release of the voltage conversion circuit 120 from the stand-by state. Therefore, when the voltage conversion circuit 120 is used in semiconductor devices, such as semiconductor memory devices, high-speed data read is unlikely to be achieved.
According to an aspect of the present invention, a voltage conversion circuit for converting the voltage of an input signal to the voltage of an output signal is provided. The circuit comprises a logic circuit for outputting an operation signal obtained by inverting and delaying the input signal based on a stand-by/operation control signal and an inverted signal having a polarity inverse to the stand-by/operation control signal or a stand-by signal obtained by delaying the input signal relative to the inverted signal based on the inverted signal; and a voltage output circuit for starting generating the output signal based on the input signal and the inverted signal before receiving the operation signal or the stand-by signal output by the logic circuit.
In one embodiment of this invention, the voltage conversion circuit further comprises a control circuit for generating the stand-by/operation control signal.
In one embodiment of this invention, the voltage conversion circuit further comprises an inversion circuit for generating the inverted signal by inverting the stand-by/operation control signal.
In one embodiment of this invention, the control circuit comprises a first inversion control circuit for generating the inverted signal; and a second inversion control circuit for generating the stand-by/operation control signal by inverting the inverted signal.
In one embodiment of this invention, the logic circuit comprises a ternary logic circuit for generating the operation signal corresponding to the input signal based on the stand-by/operation control signal and the inverted signal; and a pull-up circuit for generating the stand-by signal based on the inverted signal.
In one embodiment of this invention, the ternary logic circuit comprises a first P-type MOS transistor having a gate terminal through which the input signal is input, a source terminal, and a drain terminal; a second P-type MOS transistor having a gate terminal through which the stand-by/operation signal is input, a source terminal connected to a power source, and a drain terminal connected to the source terminal of the first P-type MOS transistor; a first N-type MOS transistor having a gate terminal through which the input signal is input, a source terminal, and a drain terminal connected to the drain terminal of the first P-type MOS transistor; and a second N-type MOS transistor having a gate terminal through which the inverted signal is input, a source terminal connected to ground, and a drain terminal connected to the source terminal of the first N-type MOS transistor. The first P-type MOS transistor and the first N-type MOS transistor function as a CMOS inverter.
In one embodiment of this invention, the voltage output circuit comprises a third P-type MOS transistor having a gate terminal, a source terminal connected to a power source, and a drain terminal; a fourth P-type MOS transistor having a gate terminal, a source terminal connected to the power source, and a drain terminal connected to the gate terminal of the third P-type MOS transistor; a third N-type MOS transistor having a gate terminal through which the inverted signal is input, a source terminal, and a drain terminal connected to the drain terminal of the third P-type MOS transistor; a fourth N-type MOS transistor having a gate terminal through which the input signal is input, a source terminal connected to ground, and a drain terminal connected to the source terminal of the third N-type MOS transistor; and a fifth N-type MOS transistor having a gate terminal through which the operation signal or the stand-by signal is input, a source terminal connected to ground, and a drain terminal connected to the drain terminal of the third P-type MOS transistor.
In one embodiment of this invention, the voltage output circuit further comprises a first output terminal and a second terminal; and the polarity of an output signal output through the first output terminal is opposite to the polarity of an output signal output through the second output terminal.
According to another aspect of the present invention, a semiconductor device incorporating the above-described voltage conversion circuit is provided.
Functions of the above-described configuration will be described below.
In the voltage conversion circuit of the present invention, the voltage output circuit starts generating an output signal based on an input signal and an inverted signal before receiving an operation signal or a stand-by signal output by the logic circuit. Thus, the signal waveform of an output signal of the voltage conversion circuit starts transition in response to the transition of the signal waveforms of the input signal and the inverted signal, thereby making it possible to reduce a delay time.
Thus, the invention described herein makes possible the advantages of providing a voltage conversion circuit having a reduced delay time of a signal between input and output terminals and a semiconductor device using the same.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.